Temperature sensitivity of GaSb/Si/SiGe Heterojunction Vertical Nanowire Junctionless Field-Effect Transistor for Logic Circuit Applications.
Micro and Nanostructures Volume 199 Article 208071(2025)—peer-reviewed, Scopus/SCI
Dr. Nishant Srivastava
Assistant Professor•Department of Electronics & Communication Engineering
14.8 Yrs
Teaching Experience
16.5 Yrs
Total Experience
Ph.D.
Highest Qualification
4+
Published Works
About & Biography
I am Assistant Professor in the Department of Electronics and Communication Engineering with 16.5 years of teaching and industry experience. I holds a Ph.D., M.Tech., and B.Tech. My research interests include Nanoelectronics, FinFETs, TFETs, and Semiconductor Device Modelling. I have published research papers in reputed journals and conferences and is a professional member of IEEE, ISTE, IAENG, and other organizations.
Education & Qualifications
Doctorate2025
Ph.D.
VLSI
SRM Institute os Science and Technology
Masters2012
M.Tech
VLSI
SRM Institute os Science and Technology
Research Specialization & Focus Areas
- VLSI & Embedded Systems
Scholarly Publications
4 publications
2025
Lateral Si/Si1- xGex/Si Channel Heterostructure Charge Plasma Nanowire JLFET to Eliminate the Effects of Variation of Geometrical Dimensions
International Journal of Numerical Modelling: Electronic Networks, Devices and Fields Volume 38, Issue2—peer-reviewed, Scopus/SCI
2024
Design and Investigation of Junctionless N+ Pocket Doped Vertical –TFET with Binary Metal Alloy PαQ1- α
IEEE Conference (2024)—Conference proceeding
Design and Analysis of a GaSb Hetrojunction Vertical TFET with Source Pocket for Work Function Engineering and Improved Analog Performance
IEEE—Conference proceeding
Honors, Awards & Recognitions
ICMETE Conference
2025